In all instances, the DS2406 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain or 3-state outputs. The 1-Wire port of the DS2406 is open drain with an internal circuit equivalent to that shown in Figure 11. Typical bus master ports are shown in Figure 12. If a bi-directional pin is not available, separate output and input pins can be tied together. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second. For normal communication excluding EPROM programming the 1-Wire bus requires only a pull-up resistor of approximately 5 kΩ for short line lengths.
The idle state for the 1-Wire bus is high. If, for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 µs, one or more of the devices on the bus may be reset. If the 1-Wire bus remains low for more than 5 ms any DS2406 that is not VCC powered may perform a power-on reset and switch off both PIOs.
TRANSACTION SEQUENCE
The sequence for accessing the DS2406 via the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory or Channel Access Function Command
Transaction/Data
17 of 30
DS2406
DS2406 EQUIVALENT CIRCUIT Figure 11
1-Wire Interface
PIO Channel
Activity
Edge
Latch "1" Detector
DATA
RX
to PIO-
Q
D
PIO
Control
Q
Reset
5 µA
10 M Ω
Typ.
TX
D
Q
Typ.
1-Wire DATA
100 Ω
from PIO-
Q
MOSFET
Control
R
Ground
Ground
Channel
Flip-Flop
BUS MASTER CIRCUIT Figure 12
A) Open Drain
VPUP
12V
DD
V
VP0300L
BUS MASTER
OR
10 k Ω
10 k Ω
VP0106N3
DS5000 OR 8051-
S
OR
EQUIVALENT
5 k Ω
BSS110
Open Drain
D
Port Pin
RX
S
D
to data connection
D
2N7000
D
470 pF
of DS2406
TX
PGM
S
S
Capacitor added to reduce
2N7000
coupling on data line due to
2N7000
programming signal switching
The interface is reduced to the 5k Ω pull-up resistor if one does not intend to program the EPROM cells.
B) Standard TTL
12V
DD
V
VPUP
(10 mA min.)
BUS MASTER
TTL-Equivalent
Port Pins
5 k
PROGRAMMING PULSE
Ω
RX
to data connection
of DS2406
TX
5 k Ω
The diode and programming circuit are not required if one does not intend to program the EPROM cells 18 of 30
DS2406
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2406 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the five ROM function commands that the DS2406 supports. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 13):
Read ROM [33h]
This command allows the bus master to read the DS2406’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used only if there is a single slave on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will be invalid.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2406 on a multidrop bus. Only the DS2406 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.
Search ROM [F0h]